With the progress in the semiconductor integrated circuits, from LSI (large scale integration), VLSI (very large scale integration), to ULSI (ultra large scale integration), the integrity of the integrated circuits rises in an amazing rate. Taking DRAM (dynamic random access memories) for example, the increasing integrity in manufacturing extends the capacity of a single DRAM chip to step from earlier 4 megabit to 16 megabit, and further to 256 megabit or even higher. The increasing integrity of integrated circuits generates numerous challenges with semiconductor manufacturing process. Every element needs to be formed within smaller area without influencing the characteristics and operations of the integrated circuits. One important challenge is in the wiring technology for forming metal connections within smaller space with uncompromising electric characteristics.
In conventional semiconductor manufacturing processes, various methods have been developed, for making a contact window within a narrow space between the gates of the device like a MOS (metal-oxide semiconductor). A SAC (self-alignment contact) technology without using a mask is now widely employed in the semiconductor manufacturing processes. The SAC technology is applied frequently in making a contact window 24 between the gates as shown in FIG. 1e. FIG. 1a shows a semiconductor substrate 10 with a gate structure 11 formed upon. The gate structure 11 has a gate oxide 12, a gate electrode 14 formed above the gate oxide, and a gate electrode protection layer 16 formed above the gate electrode. The formation of the gate structure 11 is well known in the art of semiconductor manufacturing process. The substrate 10 is prepared for proceeding following steps like forming active regions of the integrated circuits and making connections. As shown in FIG. 1b, side wall spacers 18 are then formed around the gate by sequentially depositing and anisotropically etching a first insulation layer of silicon dioxide. An ion implantation using the gate structure 11 and the side wall spacers 18 as a mask is then performed to the whole substrate 10. The uncovered spaces between the side wall spacers are ion-implanted for forming active regions such as source regions or drain regions of the integrated circuits.
A second insulation layer 20 is then covered as an IPD (inter-polysilicon dielectric) layer as shown in FIG. 1c. The second insulation layer 20 insulates the gates and other non connecting regions from making a conductive connection. The second insulation layer 20 is generally formed by depositing a silicon dioxide layer. A photoresist layer 22 is formed on the second insulation layer 20 and portions of the photoresist layer 22 is removed, for defining a connecting region as shown in FIG. 1d. An anisotropic etching process employing the photoresist layer as a mask is performed to the second insulation layer 20. Since the etching process is anisotropic, a width of a contact window 24 are defined by controlling the etching of the second insulation layer 20, as shown in FIG. 1e. The process of forming the contact window 24 is a self-aligned etching process and portions of the second insulation layer is left aside the side wall spacers 18 as second side wall spacers 20b. Finally, a connection layer 26 of doped polysilicon or metal is then deposited to fill the contact window 24 as a conductive connection to the active region, as shown in FIG. 1f.
Referring to FIG. 1e, the contact window is formed by a self-aligned, anisotropic etching of the second insulation layer. With the low exchange rate of etchant at a narrow region like the contact window 24 and under the consideration of over etching, the second side wall spacers 20b are left from incompletely etching. The presence of the second side wall spacers 20b reduce the contact window width for making a connection. The reduction in the contact window width has a great influence on the design rule controlling the space between the gates. The contact window width becomes a vital limit in raising the integrity of the integrated circuits. In addition, in the aforementioned process, the steps of etching the first insulation layer and of etching the second insulation layer 20 must be carefully controlled. Over etching during the processes may expose the gate electrode 14 at the side walls. The undesired exposing of the gate electrode 14 causes current leakage and forms unexpected short connections with a connection layer formed later. The leakage and short connections decrease the reliability or even crash some devices of the semiconductor. The process must be well controlled, or the undesired short will reduce the manufacturing yield and increase the manufacturing cost. Thus a method is needed for providing better wiring technology in making wider contact window and reducing the space needed between the gates. A solution to the over etching problem is also needed for increasing the reliability and reducing the manufacturing cost of the integrated circuits manufacturing.